1. Field of the Invention
The present invention relates to a semiconductor manufacturing process. More particularly, the present invention relates to an interconnection process.
2. Description of Related Art
With the development of semiconductor technology, the sizes of the semiconductor devices have become smaller and smaller. As the integration degree of integrated circuits (IC) is up to a certain level, a die surface is insufficient for forming all interconnects thereon. Hence, multi-level interconnects are adopted in current very-large scale integrated (VLSI) circuits.
As regards to the current process of manufacturing a metallic interconnect, a damascene technique is often employed. In a damascene process, openings are formed in a dielectric layer in most cases, and metal is then filled in the openings to form an interconnect. Furthermore, due to the difficulties in etching copper in the current semiconductor production process, copper conductive wires are usually fabricated by implementing the damascene process instead of the conventional etching process.
In the normal damascene process, a metal hard mask layer made of titanium nitride (TiN) is formed on a dielectric layer and a dielectric hard mask layer is formed on the metal hard mask layer before performing an etching process to form openings. Next, a first etching process is carried out in a first reaction chamber to pattern the dielectric hard mask layer. Afterwards, a second etching process is implemented with use of the patterned dielectric hard mask layer as a mask in a second reaction chamber to pattern the metal hard mask layer. Thereafter, another etching process is performed with use of the patterned dielectric hard mask layer and the patterned metal hard mask layer as a mask to form the opening in the dielectric layer.
Besides, to simplify the etching process in the aforementioned fabrication, a SiON layer may be formed on the metal hard mask layer, and the SiON layer and the metal hard mask layer are respectively etched with use of a CF4-containing etching gas and a Cl2-containing etching gas in one reaction chamber, so as to form a patterned SiON mask layer and a patterned metal hard mask layer. Thereafter, another etching process is performed with use of the patterned SiON mask layer and the patterned metal hard mask layer as a mask to form the opening in the dielectric layer.
However, since the CF4-containing etching gas and the Cl2-containing etching gas are utilized to respectively etch the SiON layer and the metal hard mask layer in the reaction chamber, a fluorinated polymer and a chlorinated polymer may be simultaneously generated in the reaction chamber, impairing the particle performance during the etching process and adversely affecting the subsequent manufacturing process.